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#91 (permalink) |
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Hi all,
This might sound silly. After reading about what everyone has said, To those who contributed to this thread, Be it a negative or positive response, its been very interesting. ![]() I too would like to try and program. I have a card,umm looks like Rom 10. My first question is "can i use the cas 3 plus" to emulate the hardware required to begin programing.? I Also have a book on numbering systems,computer architecture,with assembly language.To add to this a guide to Avr Development, Avr studio 4 is there anything else i requireto Help me get started. |
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#92 (permalink) | |
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The problem with the logger is that its not a particularly good tool for logging error conditions as its internal programming filters out things that dont make sense. All you see is good communications packets. So, all you can infer from the present log is that there are repeated IFS attempts which likely means that the card is being reset prior to those IFS attempts. Any problem is obviously occuring before the reset and thus before the IFS attempts. |
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#93 (permalink) |
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is it a change in baud rate?
ie, the box wants a baud rate from the card which is different from what its set to send at?
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#94 (permalink) | |
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Not there yet but definately moving in the right direction. Forget the individual commands and look at the basic data transmission system ! |
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#95 (permalink) | |
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#96 (permalink) | |
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Last edited by PaddyBhoy; 01-11-09 at 01:15 AM. |
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#97 (permalink) |
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Quick lesson in how single wire I/O operates at the physical (electrical level)
Both box and card contain both a serial transmitter and receiver device connected to the same physical wire. Now, oviously, there is a conflict here because if both box and card start to transmit at the same time then you have the possibility of an electrical "short" circuit (when one device is transmitting logic 1 whilst the other is, at the same time, transmitting a logic 0). To remove the possibility of this electrical conflict both devices use whats called an open-collector I/O port. This means the port is capable only of driving to a logic 0 state. When the I/O tries to drive to a logic 1 state there is no output. In order for there to be any logic 1 on the wire a system called passive logic high is used. This basically means that a fairly high value resistor is connected from the I/O wire to a voltage supply so that when no device is driving the line it "floats" to a logic 1 condition. So, now you have a system where either the box or the card can drag the I/O line to logic 0 only. If either device outputs a logic 0 then the line will be at logic 0. If neither device outputs a logic 0 then the line will passively rise to the loogic 1 level. Thus no possibility of an electrical "short" ! ok, thats the basic electrical protocol sorted. Now, on top of that you effectively have a master/slave software protocol where the stb is the master device and the card is the slave. The card can only output data when asked to do so by the master (the ATR is a special form of request that involve another I/O line called the reset pin). So, now you have - Box request (21 type packet) Card reply (12 type packet) The card cannot ever reply until its queried ! To keep things ticking along, both box and card will expect things to occur within certain timing tolerances. For instance the box will wait for a predefined period after sending a query before assuming the card isn't going to reply (timeout). The box will also wait for another predfined timeout after seeing a response before sending another query. There are quite a few different combinations of timeout for various conditions. Most of these timeouts are handled by the box. The card really doesn't worry about them too much - it just has to respond within the correct timeframe. ps. This is just a background in the low level operation of the protocol. Its not meant to indicate where the fault lies but it may help you to understand the functioning of the funcard program !!! Last edited by TheCoder; 01-11-09 at 01:58 AM. |
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#98 (permalink) |
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Looking at both those hexes and thinking about how data is communicated it seems that when the bit is in the register and set, it is quicky outputed all at once/packets, where as the other one isnt....
might go and play some xbox now cause I need just ot have some time to think abot this and hopefully it will just pop into my head while playing about. |
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#100 (permalink) | |
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