Intel announces 1 teraflop processor

'Knights Corner' will feature in excess of 50 cores
Kerry Butters

November 17, 2011
Intel Logo

Intel have unveiled details about their next-generation processors designed for high-performance computing (HPC) at this year’s International Supercomputing Conference.

Intel’s Rajeeb Hazra spoke at the conference about the Intel Xeon processor E5 family, which he described as the world’s first “server processor to support full integration of the PCI Express 3.0 specification.”

PCI Express 3.0 is thought to double the bandwidth over PCI Express 2.0 and enables “lower power and higher density server implementations.”

Benchmarking tests have revealed that the Xeon E5 delivers up to 70% better performance than its predecessor.

“Customer acceptance of the Intel Xeon E5 processor has exceeded our expectations and is driving the fastest debut on the TOP500 list of any processor in Intel’s history,” said Hazra.

“Collecting, analyzing and sharing large amounts of information is critical to today’s science activities and requires new levels of processor performance and technologies designed precisely for this purpose.”

The processor is intended to power supercomputers at various research centres across the US.

In a presentation given at the conference, the silicon “Knights Corner” co-processor proved that “Intel architecture is capable of delivering more than 1 TFLOPs of floating point performance”.

“This was the first demonstration of a single processing chip capable of achieving such a performance level,” Intel said.

“Intel first demonstrated a Teraflop supercomputer utilizing 9,680 Intel Pentium Pro Processors in 1997 as part of Sandia Lab’s ‘ASCI RED’ system,” Hazra said.

“Having this performance now in a single chip based on Intel MIC architecture is a milestone that will once again be etched into HPC history.”

Knights Corner is Intel’s first venture into a commercial MIC architecture product and is expected to feature more than 50 cores.

The processor is unique in that it is fully programmable and is “visible to applications as though it was a computer that runs its own Linux-based operating system independent of the host OS.”

Intel had previously announced that their goal is to deliver Exascale-level performance by 2018.

Exascale-level performance is thought to achieve speeds which are more than 100 times faster than are currently available.

The company have signed a deal with Barcelona Supercomputing Centre in order to create an Exascale research and development lab in Barcelona, which will focus on the programming and runtime systems of Exascale supercomputers.

Intel will also develop and test technology for the supercomputers of the future at Daresbury Lab in the UK, under an agreement with the Science and Technology Facilities Council (STFC).






 

Post a comment

Your email address will not be published. Required fields are marked *

Visited 2980 times, 1 so far today